1. Field of the Invention
The present invention relates to circuits for sampling a digital (digitized) signal.
2. Description of Related Art
Patent publication WO 9918691 of the present assignee (corresponding to allowed U.S. application Ser. No. 09/006,938 entitled DIGITAL PHASE DISCRIMINATION BASED ON FREQUENCY SAMPLING, filed 14 Jan. 1998, incorporated herein by reference) describes a digital circuit for forming number streams for representing frequency and/or phase of digital or digitized signals, referred to herein as clock signals, where typically one of the clock signals is a known clock signal and another of the clock signal is an unknown clock signal. The unknown clock signal may be derived from a communications signal, for example. Referring to FIG. 1, In the illustrated embodiment, it is assumed that the ratio of the clock signals is such that no more than one rising edge of the faster clock will occur during a single period of the slower clock. In other embodiments, this assumption need not apply.
The capture circuit includes an input portion 101 and an output portion 103. The input portion includes two sections Ch1 and Ch2 that must be carefully matched to minimize errors. Each section comprises a chain of two or more D flip-flops coupled in series. In the following description, the same reference numerals will be used to reference the respective flip-flops themselves and their respective output signals.
Within each section, the first flip-flop in the chain is clocked by a sampled clock signal Fx. The succeeding flip-flops in the chain are clocked by a sampling clock signal Fs. The D input of the first flip-flop Q1 in the upper section is coupled to the Qb output of the same. The D input of the first flip-flop in the lower section is coupled to the Q output of the first flip-flop in the upper section. The remaining flip-flops in both sections are coupled in series—i.e., Q to D, Q to D.
The function of the input portion is to 1) produce two signals, logical inverses of one another, that transition on rising edges of the clock signal Fx; 2) to latch the values of the two signals on the rising edge of the clock signal Fs; and 3) to detect transitions from one clock to the next. The intermediate stages Q3 and Q4 may be required to minimize metastability resulting from the asynchrony of the two clock signals, and in fact multiple such stages may be desirable in a particular design.
The output portions includes, in an exemplary embodiment, three two-input NAND gates. Respective NAND gates N1 and N2 are coupled to the D and Q signal of the final flip-flop stages of the input sections. Output signals of the NAND gates N1 and N2 are combined in the further NAND gate N3 to form the final output of the capture circuit.
The function of the output portion is to detect a change in the input clock signal level from one sample clock to the next in either of two channels formed by the two input sections. The two input sections function in a ping-pong fashion, alternately detecting changes in the input clock signal level.
Operation of the capture circuit of FIG. 1 may be more fully appreciated with reference to the timing diagram of FIG. 2. The first stages of the two channels form inverse signals Q1 and Q2 approximately coincident with (but slightly delayed from) rising edges of the input clock signal. The signals Q3 and Q4 are formed by sampling the signals Q1 and Q2, respectively, in accordance with the sample clock. The signals Q5 and Q6, respectively, are delayed replicas of the signals Q3 and Q4. The NAND gates together realize the logic function X=Q3.Q5v Q4.Q6.
In the example of FIG. 2, the illustrated signals are all idealized squarewave signals. In actuality, the signals will have finite rise and fall times. The possible effect of the finite rise and fall times of the signals Q1 and Q2 and the asynchrony of the circuit is metastability, as illustrated in FIG. 3. Here, the signals Q3 and Q5 and the signals Q4 and Q6 are each in an indeterminate state for one cycle. The resulting output of the circuit may or may not be correct. However, because the decision was a “close call” to begin with, the effect of an occasional erroneous decision on the overall operation of the circuit is negligible. The time window of instability is reduced by increasing the overall gain in the path. If the gain in Q3 and Q4 is sufficient to reduce the probability of an error to an acceptable level, then no additional circuitry is required. If not, then additional circuitry will be required to increase the gain.
In some applications, it is desirable that rate of the unknown clock signal be allowed to exceed the rate of the known clock signal. The foregoing circuit does not satisfy this requirement.